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05_UsingAccelWare
- This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each
DSP-c-Matlab-Programs-ManualV19
- 印度GURUNANAK ENGINEERING COLLEGE数字信号处理实验室的DSP+c+Matlab联合编程手册-DIGITAL SIGNAL PROCESSING LAB (IV-I SEM) INDEX 1. Architecture of DSP chips-TMS 320C 6713 DSP Processor 2. Linear convolution 3. Circular convolution 4. FIR Filter (LP/HP) Using Wi
WatchForLab
- This was the first lab assigmnet in the course CPU Architecture, creat a basic watch
lab
- 系统结构实验报告，WinDLX模拟器是一个图形化、交互式的DLX流水线模拟器，能够演示DLX流水线是如何工作的。该模拟器可以装载DLX汇编语言程序（后缀为“.s”的文件），然后单步、设断点或是连续执行该程序。CPU的寄存器、流水线、I/O和存储器都可以用图形表示出来，以形象生动的方式描述DLX流水线的工作过程。模拟器还提供了对流水线操作的统计功能，便于对流水线进行性能分析。-Computer Systems Architecture Lab
lab1
- lab session for computer architecture basics such as binary etc.
lab2
- Lab 2 for computer architecture more basics are in here, so check them out!
jspPageControlor
- jspPageControlor分页插件是千里web架构实验室成员--刘捷开发的插件,用来解决jsp程序设计中分页所带来的不便，让程序开发者轻松的实现分页功能。-jspPageControlor web page plug-in architecture lab members are thousands of miles- Liu Jie, the development of plug-ins, programming to solve the jsp page inconvenience,
EPM240ZT100
- The MAX II CPLD has the following features: ■ Low-cost, low-power CPLD ■ Instant-on, non-volatile architecture ■ Standby current as low as 29 μA ■ Provides fast propagation delay and clock-to-output times ■ Provides four global clocks with
computer-architecture-lab
- this document explain the majors of VERILOG language in a very efficient and briefly manner.this is very useful to learn about hardware design and implementing them by FPGAs.
Xilinx_ISE_PPT(whole)
- Xilinx_ISE_大学计划使用教程PPT(全) Xilinx_ISE_大学计划使用教程PPT_1包括：Xilinx公司产品概述，Xilinx公司软件平台介绍，Xilinx公司ISE10.1软件 设计流程介绍，PicoBlaze的8位微控制器概述，PicoBlaze的简单处理解决方案，PicoBlaze的一个实例，PicoBlaze指令集详解； Xilinx_ISE_大学计划使用教程PPT_2包括： PicoBlaze指令集详解，KCPSM3 汇编器，KCPSM3编程语法，KCPS
FPGA-Train
- FPGA基础培训，包括： FPGA基本架构 Xilinx工具流程 实验1：Xilinx工具流程演示 实验2：架构向导和PACE 实验3：全局时序约束 实验4：合成技术 实验5：CORE Generator系统 实验6：利用ChipScope-PRO-Basic FPGA Architecture Xilinx Tool Flow Lab 1: Xilinx Tool Flow Demo Architecture Wizard and PACE L
LTE_Link_Level_Simulator_Vehicom
- Vehicom LTE Link Level Simulator -The LTE link level simulator is a comprehensive simulation software used for algorithm development, performance evaluation and system validation associated with LTE systems. The simulator have Matlab and C versions.
lab-assignment1
- 这个是计算机结构的实验内容,主要包括逻辑门的设计(例如:与门,或门,非门).此外还有testbench的设计代码.-This is a computer architecture in experiments, including the design of logic gates (for example: AND gates, OR gates, NAND gate). Addition testbench design code.
parta
- Architecture Lab Part A，计算机系统导论实验作业-Architecture Lab Part A
partb
- Architecture Lab Part B，计算机系统导论实验作业-Architecture Lab Part B
partc
- Architecture Lab Part C，计算机系统导论实验作业 CPE=8.5-Architecture Lab Part C CPE=8.5
partc-6.1
- 计算机系统导论 Architecture Lab Part C CPE=6.1-Architecture Lab Part C CPE=6.1
Debug
- 软件体系结构实验报告采用面向对象体系架构风格实现KWIC关键词索引系统-Software architecture lab report using object-oriented architecture style keyword indexing system to achieve KWIC
lab
- 本程序实现了学生上机实验管理系统，用jsp+MySQL 架构编写，实现了老师在线发布实验作业 ，评改实验作业，和与学生交流的功能。学生可以产看作业和提交作业，查看成绩等等。-The program implements a student machine experiment management system, written in jsp+ MySQL architecture to achieve a teacher online publishing lab assignments, a
archlab_solution
- architecture lab soultion